AR# 47735: FIFO Generator v9.1- ISE 14.1/VIVADO 2012.1 - Release Notes and Known Issues for ISE
AR# 47735
FIFO Generator v9.1- ISE 14.1/VIVADO 2012.1 - Release Notes and Known Issues for ISE
Description
This Release Notes and Known Issues Answer Record is for the FIFO Generator v9.1 Core, released in ISE 14.1 software and contains the following information:
This Article contains the following sections:
1. Introduction 2. New Features 2.1 ISE 2.2 Vivado 3. Supported Devices 3.1 ISE 3.2 Vivado 4. Resolved Issues 4.1 ISE 4.2 Vivado 5. Known Issues 5.1 ISE 5.2 Vivado 6. Technical Support
2.1 ISE - ISE 14.1 software support - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL, and Automotive Zynq device support - Data width support up to 4096 for AXI FIFO - Support of programmable Full/Empty flags as sideband signals for AXI FIFO
2.2 Vivado - 2012.1 software support - Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL, and Automotive Zynq device support - Data width support up to 4096 for AXI FIFO - Support of programmable Full/Empty flags as sideband signals for AXI FIFO
3.1 ISE The following device families are supported by the core for this release.
All 7 Series devices Zynq-7000 devices All Virtex-6 devices All Spartan-6 devices All Virtex-5 devices All Spartan-3 devices All Virtex-4 devices 3.2 Vivado All 7 Series devices Zynq-7000 devices
The following are known issues for v9.1 of this core at time of release:
1. Importing an XCO file alters the XCO configurations Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
CR 467240 AR 31379
2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA, correct behavior of the FIFO status flags cannot be guaranteed after the first write. Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
For more information and additional workaround see Answer Record 41099.
5.2 Vivado - N/A
Technical Support
To obtain technical support, create a WebCase at www.xilinx.com/support. Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.