UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - Adaptable. Intelligent.
  2. Support
  3. AR# 47815: Vivado Constraints - How do I convert an ISE FROM:TO: value constraint to XDC?

AR# 47815

Vivado Constraints - How do I convert an ISE FROM:TO: value constraint to XDC?

Description

How do I convert the following ISE FROM:TO constraint to XDC?

NET "clk_rx" TNM_NET = "TNM_clk_rx";
NET "clk_tx" TNM_NET = "TNM_clk_tx";
TIMESPEC TS_clk_rx_to_clk_tx = FROM "TNM_clk_rx" TO "TNM_clk_tx" 5 ns;
TIMESPEC TS_clk_tx_to_clk_rx = FROM "TNM_clk_tx" TO "TNM_clk_rx" 5 ns;

Solution

If this FROM:TO is to be a multi-cycle (for example, 2x the period) constraint, then use the following:

set_multicycle_path -from [all_fanout -from [get_nets clk_rx] -flat -endpoints_only] -to [all_fanout -from [get_nets clk_tx] -flat -endpoints_only] -setup 2
set_multicycle_path -from [all_fanout -from [get_nets clk_rx] -flat -endpoints_only] -to [all_fanout -from [get_nets clk_tx] -flat -endpoints_only] -hold 1
set_multicycle_path -from [all_fanout -from [get_nets clk_tx] -flat -endpoints_only] -to [all_fanout -from [get_nets clk_rx] -flat -endpoints_only] -setup 2
set_multicycle_path -from [all_fanout -from [get_nets clk_rx] -flat -endpoints_only] -to [all_fanout -from [get_nets clk_tx] -flat -endpoints_only] -hold 1

If clk_rx and clk_tx are clocks and have period constraints (for example, create_clock constraints with -name clk_rx/clk_tx), the set_multicycle_path constraints can also be:

set_multicycle_path -from [get_clocks clk_rx] -to [get_clocks clk_tx] -setup 2
set_multicycle_path -from [get_clocks clk_rx] -to [get_clocks clk_tx] -hold 1
set_multicycle_path -from [get_clocks clk_tx] -to [get_clocks clk_rx] -setup 2
set_multicycle_path -from [get_clocks clk_tx] -to [get_clocks clk_rx] -hold 1

If this FROM:TO is to be an explicit requirement, then use the following:

set_max_delay -from [all_fanout -from [get_nets clk_rx] -flat -endpoints_only] -to [all_fanout -from [get_nets clk_tx] -flat -endpoints_only] 5
set_max_delay -from [all_fanout -from [get_nets clk_tx] -flat -endpoints_only] -to [all_fanout -from [get_nets clk_rx] -flat -endpoints_only] 5

If clk_rx and clk_tx are clocks and have period constraints (for example, create_clock constraints with -name clk_rx/clk_tx), the set_max_delay constraints can also be:
 

set_max_delay -from [get_clocks clk_rx] -to [get_clocks clk_tx] 5
set_max_delay -from [get_clocks clk_tx] -to [get_clocks clk_rx] 5


Note: the example in this Answer Record is not applicable for all designs.

Users are responsible for validating their design constraints.

For more information on the ISE FROM-TO Constraint, please refer to UG625 and UG612.

For more information on Vivado set_multicycle_path and set_max_delay constraints, please refer to UG903.
AR# 47815
Date 10/15/2014
Status Active
Type General Article
Tools
  • Vivado Design Suite
Page Bookmarked