The following answer records represent a collection of issues that have been identified in the ISE 14.x and Vivado 2012.x design tools and are related to 7 series FPGAs.
General
| (Xilinx Answer 43347) | Kintex-7 FPGA Initial Engineering Sample (ES) Master Answer Record and Known Issues |
| (Xilinx Answer 45696) | Kintex-7 - General Engineering Sample (ES) Master Answer Record and Known Issues |
| (Xilinx Answer 43423) | Virtex-7 Initial ES Known Issues Master Answer Record |
| (Xilinx Answer 44971) | 7 Series XADC - Accuracy of On Chip Reference |
| (Xilinx Answer 45781) | 7 Series XADC - INL Specification Information |
| (Xilinx Answer 41615) | 7 Series, BitGen (13.2 and later) - "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)" |
Development Boards
| (Xilinx Answer 45382) | Virtex-7 FPGA VC707 Evaluation Kit - Known Issues and Release Notes Master Answer Record |
| (Xilinx Answer 45934) | Kintex-7 FPGA KC705 - Known Issues and Release Notes Master Answer Record |
7 Series Transceivers - GTP, GTX, GTH, GTZ
| (Xilinx Answer 50827) | 7 Series FPGAs Transceiver Wizard v2.2 - Known Issues and Release Note |
| (Xilinx Answer 46048) | 7 Series FPGA Transceivers Wizard - Which silicon revisions are supported by different Wizard or ISE/Vivado tool versions? |
ChipScope
| (Xilinx Answer 47769) | 14.x ChipScope Pro and 2012.x Vivado Debug - Known Issues for the 14.x ChipScope Pro and 2012.x Vivado Debug tools |
MIG
| (Xilinx Answer 45195) | MIG 7 Series - Release Notes and Known Issues for All Versions |
Integrated Block for PCI Express
| (Xilinx Answer 40469) | 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions |
| (Xilinx Answer 47441) | Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for All Versions |
Additional Information
To find the generic list of known issues for ISE Design Suite 14.x, see the Xilinx Design Tools: Release Notes Guide (UG631).
For information on how to download, install, and obtain a license for ISE Design Suite 14.x, see the Xilinx Design Tools: Installation and Licensing Guide (UG798).
| (Xilinx Answer 42944) | Design Advisory Master Answer Record for Virtex-7 FPGA |
| (Xilinx Answer 42946) | Design Advisory Master Answer Record for Kintex-7 FPGA |
| (Xilinx Answer 47916) | Zynq-7000 SoC Devices - Silicon Revision Differences |
| (Xilinx Answer 51456) | Design Advisory Master Answer Record for Artix-7 FPGA |
| (Xilinx Answer 50906) | Design Advisory for Production Kintex-7 325T, 410T, 420T and Virtex-7 485XT - Bitstream compatibility requirements between GES and Production devices |
Revision History
| 02/05/2013 | Updates for 14.x/2012.x design tools release |
| 10/22/2012 | Updates for 14.3/2012.3 design tools release |
| 07/25/2012 | Updated for 14.2 and 2012.2 design tools release |
| 05/09/2012 | Initial release |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 47397 | Vivado Design Suite 2012 - Known Issues | N/A | N/A |
| 51901 | Virtex-7 FPGA VC709 Connectivity Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
| 45382 | Virtex-7 FPGA VC707 Evaluation Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
| 51900 | Artix-7 FPGA AC701 Evaluation Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 51192 | Artix-7 FPGA Initial Engineering Sample (IES) - Known Issues Master Answer Record | N/A | N/A |