UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - All Programmable
  2. Support
  3. AR# 47823: LogiCORE IP Serial RapidIO Gen2 v1.4 - how to recognise a CRC Error

AR# 47823

LogiCORE IP Serial RapidIO Gen2 v1.4 - how to recognise a CRC Error

Description

The LogiCORE IP Serial RapidIO Gen2 v1.4 core has an additional port for debugging as described in (Xilinx Answer 47191)

However, it does not include the CRC Error port.

How should I know if a CRC error occurs?

Solution

If the following is true, there is a CRC error:

PR_debug[160] &&phy_debug[196:192] == h04

-

PR_send[160]: Send PNA( OLLM Rx detects the condition for sending PNA)

phy_debug[196:192]:cause field for outgoing PNAs

AR# 47823
Date 11/19/2014
Status Active
Type General Article
IP
  • Serial RapidIO
Page Bookmarked