AR# 47868: LogiCORE SPI-4.2 (POS-PHY L4) - DRC Error when TSClk uses Global Clocking and Performance >= 1 Gb/s
AR# 47868
LogiCORE SPI-4.2 (POS-PHY L4) - DRC Error when TSClk uses Global Clocking and Performance >= 1 Gb/s
Description
When implementing a SPI-4.2 core for Virtex-6, Kintex-7 or Virtex-7 design with a core configuration that uses TSClk clock distribution = global clocking and Performance >= 1Gbps, you may get the following DRC error:
Error Invalid attribute value - <no location> The configured VCO frequency is out of range for Cell pl4_src_clk0/mmcm1. Valid FVCO range varies depending on speed grade: 600MHz - 1200MHz(-1), 600MHz - 1440MHz(-2), 600MHz - 1600MHz(-3). The computed FCVO is a function of the input frequency CLKIN1_PERIOD, the division factor DIVCLK_DIVIDE, and the CLKFBOUT_MULT_F attribute (FVCO = 1000*CLKFBOUT_MULT_F/(CLKIN1_PERIOD*DIVCLK_DIVIDE)). The CLKIN1_PERIOD attribute is set to the clock constraint value on the CLKIN1 period or can be set as an attribute in HDL. Please adjust the CLKIN1_PERIOD, CLKFBOUT_MULT_F or DIVCLK_DIVIDE attributes to configure the Cell's VCO frequency to be within the valid range. Related violations: <none>
Solution
1. Open the pl4_src_clk.v/vhd file and edit the attribute to the MMCM that generates the internal TSClk (instance name mmcm1). 2. Change the CLKFBOUT_MULT_F and CLKOUT0_DIVIDE_F value from 9 to 7.