AR# 47924


MIG 7 Series Solution Center - Design Assistant - DDR3 Jedec Specification - ZQ Calibration


This section of the MIG Design Assistant focuses on the ZQ Calibration defined by the JEDEC Specification, as it applies to the MIG 7 Series FPGA DDR3 designs.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


ZQ Calibration Commands are required to calibrate the DRAM ODT and Ron values. The DRAM requires a longer time to perform this calibration during initialization (ZQCL) and a shorter period of time after initialization (ZQCS). The MIG 7 Series design includes both ZQ Short (ZQCS) and ZQ Long (ZQCL) Calibration commands that adhere to the DDR3 JEDEC Standard. The ZQ Calibration Command is discussed in section 5.5 of JEDEC Specification JESD79-3 DDR3 SDRAM Standard.

The ZQ Short Calibration command allows the on die termination (ODT) to be calibrated at regular intervals to account for variations across voltage and temperature. As defined by the JEDEC standard, the interval between ZQCS commands should be determined by:

(TSens x Tdriftrate) + (VSens x Vdriftrate)

The MIG 7 Series design by default sets this interval to 128 ms usingan automated timer defined by the top level parameter tZQI. A user can choose a different interval based on VT drift characteristics of the unit.

User requested ZQCS command

In place of the automated timer ZQ Short Calibration command, the user design can send explicitly the command at convenient timing. The assertion of app_zq_req issues one ZQCS command. Thereturn ofapp_zq_ack acknowledges the command was issued. Using this command while the DDR bus is idle can optimize the bandwidth and read/write timing.

Revision History
9/7/2012 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51684 MIG 7 Series DDR2/DDR3 - JEDEC Specification N/A N/A
34243 Xilinx Memory Interface Solution Center N/A N/A
34941 MIG 7 Series and Virtex-6 DDR2/DDR3 - User Interface - DDR Commands N/A N/A
AR# 47924
Date 09/18/2012
Status Active
Type Solution Center
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