UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47938

Design Advisory for 14.1 Timing Analysis Virtex-6 - Tioop/Tiotp values have increased in the analysis of OFFSET OUT and FROM:TO constraints

Description

I ran timing analysis in ISE Design Suite 14.1 and noticed that the Tioop and Tiotp timing delays increased. Also, it appears that the "Timing Score" increased. Why did this change?

Solution

These timing delays did increase to include the I/O Standard adjustment delays and may impact the final "Timing Score." The IOB contains the PAD, ILOGIC, and OLOGIC, so a simple FF (OFF) to PAD path does include the Tioop timing delay. The I/O Standard adjustment is added to both process corners and min/max in both corners, so the majority of the output data paths will see an increase in delays. The data paths associated with the OBUF T -> O and OBUF I -> O paths will see an increase in delays.

The timing delay Tioop was incorrectly impacted by this change and will be fixed in ISE Design Suite 14.2.

The timing delay Tiotp was corrected changed in 14.1.

This is a Timing Analysis software issue and not a data sheet change. Xilinx recommends re-timing your design to determine if this delay increase impacts your timing score.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
40835 Design Advisory for Xilinx Timing Solution Center N/A N/A
34565 Design Advisory Master Answer Record for Virtex-6 FPGA N/A N/A
AR# 47938
Date Created 05/17/2012
Last Updated 05/22/2012
Status Active
Type Design Advisory
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Virtex-6QL
  • Less
Tools
  • ISE Design Suite - 14.1