These timing delays did increase to include the I/O Standard adjustment delays and may impact the final "Timing Score." The IOB contains the PAD, ILOGIC, and OLOGIC, so a simple FF (OFF) to PAD path does include the Tioop timing delay. The I/O Standard adjustment is added to both process corners and min/max in both corners, so the majority of the output data paths will see an increase in delays. The data paths associated with the OBUF T -> O and OBUF I -> O paths will see an increase in delays.
The timing delay Tioop was incorrectly impacted by this change and will be fixed in ISE Design Suite 14.2.
The timing delay Tiotp was corrected changed in 14.1.
This is a Timing Analysis software issue and not a data sheet change. Xilinx recommends re-timing your design to determine if this delay increase impacts your timing score.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 40835 | Design Advisory for Xilinx Timing Solution Center | N/A | N/A |
| 34565 | Design Advisory Master Answer Record for Virtex-6 FPGA | N/A | N/A |