AR# 47943


LogiCORE IP Ten Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) v2.3 - In Asynchronous Systems the RX Elastic Buffer Can Incorrectly Empty


In the Ten Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR v2.3 core extra delay was added to the synchronization across the clock domain boundaries.

As a result of this, the occupancy level calculation lagged by a couple of cycles.

This meant that the FIFO status was reporting that the FIFO had a higher occupancy than it actually had.

As a result, the idle insertion can sometimes not be flagged and the FIFO will run empty.


The fix in the below v2.3 rev1 patch is to have the occupancy level calculated on a pipelined version of the write address to account for the read address sync stages and report the correct occupancy.

Installation/Use: This patch is for use with ISE 14.1 and Vivado 2012.1 design tools.

Install the patch below by extracting the contents of the ".zip" archive to the root directory of the XILINX (Xilinx ISE installation). 

Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure predefined in the archive.

For further information on finding the Xilinx install and using environment variable, see (Xilinx Answer 11630).

Note: You might be required to have a system administrator to install the patch if you do not have write permissions to the Xilinx Install directory.


Associated Attachments

Name File Size File Type 37 KB ZIP
AR# 47943
Date 10/17/2014
Status Active
Type Design Advisory
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