AR# 47959: 13.4 Timing Analysis Virtex-6 - Clock Arrival Times are Incorrect for Block Ram or FIFO Components
AR# 47959
13.4 Timing Analysis Virtex-6 - Clock Arrival Times are Incorrect for Block Ram or FIFO Components
Description
When I analyze the timing paths to or from the Block Ram or FIFO, the clock arrival time for either the source or destination clock is incorrect and makes the requirement extra small. I should have a full cycle for these paths. When is this going to be fixed?
Solution
This issue is resolved in ISE Design Suite 14.1, but you must re-run implementation from NGDbuild.