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  3. AR# 4799: 3.x FPGA Express - "ERROR:NgdBuild:466 - Input pad net 'clock_name' has illegal connection"

AR# 4799

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3.x FPGA Express - "ERROR:NgdBuild:466 - Input pad net 'clock_name' has illegal connection"

Description

Keywords: FPGA Express, illegal, connection, NGDBuild, basnu, PADMAP-1

Urgency: Standard

General Description:
My design has an instantiated BUFG; during synthesis, FPGA Express issues an "FE-PADMAP1" warning. When the M1 tools process the netlist, NGDBuild (Translate) reports an error similar to the following:

Checking expanded design...
ERROR:basnu:142 - Input pad net "rclk1" has an illegal connection.

Solution

This problem has been seen in two different situations.

In the first instance, the net with an illegal connection is bidirectional; in the second instance, the net is simply an input. In both cases, the BUFG is instantiated in a multiplexor arrangement. Essentially, the input to the BUFG is being driven by an external pin on the device. However, in parallel, because of the muxing structure, this input was also driving combinatorial logic.

FPGA Express recognizes that the BUFG is being driven from a PAD, so it issues the FE-PADMAP 1 warning and does not insert an IBUF. However, because the pin is also driving logic, the connection is illegal. An IBUF should be inserted to drive the combinatorial logic and the input to the BUFG.

Here is the connection that is formed:

Figure 1 - IPAD to BUFG Connection
Figure 1 - IPAD to BUFG Connection




And here is what should be formed:

Figure 2 - IPAD to IBUF to BUFG Connection
Figure 2 - IPAD to IBUF to BUFG Connection




The work-around is to manually instantiate the IBUF (as well as the BUFG) in your HDL code. This will still cause FPGA Express to issue the FE-PADMAP warning, but because the cell is an IBUF, all connections are now perfectly legal in the netlist, and design will translate correctly.
AR# 4799
Date 08/11/2003
Status Archive
Type General Article
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