General Description: When using FPGA Express to synthesize a design to a Spartan or a Spartan XL, the Express Constraints GUI is missing the "Xilinx Options" tab.
Solution
The only feature this particular tab offers for Spartan designs is to "Ignore unlinked cells during GSR mapping". This option will infer the STARTUP module if the design contains black boxes and all the synchronous logic is set/reset by a single signal.
If your design fits these conditions (Spartan/XL, black boxes, on set/reset signal), you will have to instantiate the STARTUP module in your HDL code rather than having Express infer it.