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AR# 4842

VERILOG-XL - "Warning! no matching timing check SETUP in Veritool for instance ..." - skipping annotation

Description

Keywords: Verilog-XL, setup

Urgency: Standard

General Description:
When running an M1.5 Verilog netlist through Verilog-XL, the SDF-annontator
issues warnings such as:

Highest level modules:
ping_tb
*** SDF Annotator version 1.7
*** SDF file: pcim_top_routed.sdf
*** Back-annotation scope: ping_tb.UUT
*** No configuration file specified - using default options
*** SDF Annotator log file: sdf.log
*** No MTM selection parameter specified
*** No SCALE FACTORS parameter specified
*** No SCALE TYPE parameter specified
Configuring for back-annotation...
Reading SDF file and back-annotating timing data...
*** Hierarchy divider in SDF is being mapped to `.'

"./pcim_top_routed.v", 10503: warning! no matching timing check SETUP
in Veritool for instance AD<0>\/INBLOCK\/IN_FF - skipping annotation
SDF line 5243

"./pcim_top_routed.v", 10503: warning! no matching timing check SETUP
in Veritool for instance AD<0>\/INBLOCK\/IN_FF - skipping annotation
SDF line 5244

"./pcim_top_routed.v", 10503: warning! no matching timing check HOLD
in Veritool for instance AD<0>\/INBLOCK\/IN_FF - skipping annotation
SDF line 5245

Solution

1

The X_FF.vmd model $setup check has changed from M1.4 to M1.5

M1.4

$setup( SET, posedge CLK &&& set_clk_enable, RECSETCLK) ;
$setup( RST, posedge CLK &&& rst_clk_enable, RECRSTCLK) ;

M1.5

$setup( negedge SET, posedge CLK &&& set_clk_enable, RECSETCLK) ;
$setup( negedge RST, posedge CLK &&& rst_clk_enable, RECRSTCLK) ;

Using an older version of Verilog-XL would need $setup PLI routines
to have both "negedge <pin_name> and posedge <piname>" with respect
to posedge CLK as separate calls in the Verilog SIMPRIM model.

Version 9504 (Verilog-XL 2.3.3) and above do not require this to be two
separate $setup calls, but rather just "pin_name" with respect to
posedge CLK.

Use a more up-to-date version of Verilog-XL 2.5 (97A release)
or 2.6.11 (PE 13.0 release). These versions of Verilog-XL have been
tested and support these PLI routines.

2

Another problem that may occur if you are using M1.5 Verilog/SDF netlist files;
the SIMPRIM models that you are pointing to are NOT recomplied with M1.5 Verilog
SIMPRIM.

Debug this by going to the erroneous line in the SDF file pointed out by Veritool.

There would be something like.....

(SETUP (negedge RST) (posedge CLK) (0:0:0))

Then go to the Verilog SIMPRIM that this refers to and you should see:

$setup( negedge RST, posedge CLK &&& rst_clk_enable, RECRSTCLK) ;

Every setup/hold/width check in SDF must have a corresponding
$setup/$hold/$width PLI routine for the appropriate pins in the X_*.vmd file.
AR# 4842
Date Created 08/31/2007
Last Updated 03/11/2001
Status Archive
Type ??????