AR# 4867: FPGA Express: all combinatorial logic is mapped by Express
FPGA Express: all combinatorial logic is mapped by Express
Keywords: FMAP, Express, EQN, INV, mapping, logic
General Description: When FPGA Express synthesizes a design for a Xilinx FPGA, it includes mapping information when writing the XNF file. For Virtex families this is done in the form of LUTs with INIT attributes. For all XC4000, XC5000 and Spartan families, this is done with FMAPs and HMAPs. In the XC3000, this is achieved by using EQN components to represent both logic and mapping.
This process is beneficial for both runtime and results, but there is at least one situation that hurts the final results, and that situation is when a simple inversion is mapped. Inversions are merged into surrounding logic whenever possible, but that cannot be done if the inverter is FMAPed.
There are two ways to remove the mapping from the inverter. The first is to tell MAP to remove ALL mapping from the design. This is done via the NOFMAPS environment variable.
You will see in the Map report that all the FMAP components have been trimmed.
The second way is to manually edit the XNF and remove the FMAP on that inverter. This maintains all other mapping in the design, but requires manual intervention in the netlist.
For example, if you have instantiated the STARTUP module and want to use an active low signal to drive the GSR pin, you would have something like this in your VHDL code:
N_GSR <= not RESET; STARTUP_INST: STARTUP (GSR => N_GSR);
The resulting XNF would have an inverter, and following the RESET port or the STARTUP module in the XNF you would find something like this:
SYM, c122_c0, BUF, LIBVER=2.0.0 PIN, I, I, N302, , PIN, O, O, N337, , , INV END SYM, FMAP_16, FMAP, LIBVER=2.0.0 <--first line PIN, I1, I, N302, , PIN, O, O, N337, , END <--last line
Note that the component is a BUF, not an INV. To remove the FMAP, delete the four lines noted. This will eliminate the mapping constraint and will allow MAP to merge the inversion with the STARTUP module.