General Description: To use boundary Scan in Xilinx devices, you must instantiate the boundary scan symbol (BSCAN) and the associated dedicated I/O, and use the "dont_touch" attribute; otherwise it is possible that BSCAN will be deleted by Synopsys.
Note, the code examples for instantiaing BSCAN will work with FPGA Express v2.0 or later and FPGA Compiler/Design Compiler. Note FPGA Express does not use Compiler scripts. The compile scripts only apply to the FPGA Compiler/Design Compiler flow.
Solution
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I. VHDL Code for Instantiating BSCAN in the XC5200:
-- XC5200 example of instantiating the BSCAN symbol
entity example is port (a, b: in bit; c: out bit); end example;
architecture xilinx of example is
component BSCAN port(tdi, tms, tck: in bit; tdo: out bit); end component;
component TCK port ( I : out bit ); end component;
component TDI port ( I : out bit ); end component;
component TMS port ( I : out bit ); end component;
component TDO port ( O : in bit ); end component;
component ibuf port (i: in bit; o: out bit); end component;
component obuf port(i: in bit; o: out bit); end component;
signal tck_net, tck_net_in : bit; signal tdi_net, tdi_net_in : bit; signal tms_net, tms_net_in : bit; signal tdo_net, tdo_net_out : bit;
begin
u1: bscan port map (tdi=>tdi_net, tms=>tms_net, tck=>tck_net, tdo=>tdo_net_out);
u2: ibuf port map(i=>tck_net_in, o=>tck_net); u3: ibuf port map(i=>tdi_net_in, o=>tdi_net); u4: ibuf port map(i=>tms_net_in, o=>tms_net);
u5: obuf port map(i=>tdo_net_out, o=>tdo_net);
u6: TCK port map (I=>tck_net_in); u7: TDI port map (I=>tdi_net_in); u8: TMS port map (I=>tms_net_in);
u9: TDO port map (O=>tdo_net);
process(b) begin if(b'event and b='1') then c <= a; end if; end process;
end xilinx;
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II. Verilog Code for Instantiating BSCAN in the XC4000 NOTE: VERILOG IS CASE SENSITIVE! BE SURE TO FOLLOW THE CASE USED IN THIS EXAMPLE!
//XC4000/XC4000E Example of instantiating BSCAN symbol