AR# 4891


NGDBUILD 1.4: "ERROR:basnb:79 - Pin mismatch between block ..." with Synplify 5.x


Using M1.4 together with Synplify 5.x and CORE Generator or Logiblox, I find that NGDBuild errors with this type of message: 


ERROR:basnb:79 - Pin mismatch between block "XCOUNTER", TYPE="tenths", 

and file "/home/paulo/3rd/synplicity/verilog/watch/par/" 

at pin "Q_OUT[9:0](0)". Please make sure that all pins on the 

instantiated component match pins in the lower-level design block. 

(Pin-name matching is case-insensitive.) 


The problem is that CORE Generator writes out the pin names to its EDIF netlist as individual bits, and EDIF2NGD is unable to correlate the individual bits in the CORE Generator EDIF netlist with the bus name reference in the Synplify netlist. EDIF2NGD 1.5 handles embedded ranged strings in array names. Please see (Xilinx Answer 5416).


Use M1.5 to work around the problem. M1.5 edif2ngd recognizes the following syntax: 


(port (array (rename tenthsout "TENTHSOUT[9:0]") 10) (direction OUTPUT)) 


and splits the bus accordingly into 10 scalar bits. However, pre-M1.5 versions of edif2ngd assume that the signal, "TENTHSOUT[9:0]", is 1-bit wide instead of a vector.  


Xilinx recommends using the Synplicity XNF flow for 1.4, and the EDIF flow for 1.5. The XNF format can be selected from the  

Synplify menu as follows: 


"Target -> Set device options -> Result format -> xnf" 


Please see (Xilinx Answer 4272) for details on other potential pin-mismatch issues with Synplify 5.x.


You can specify to have your bus ports expanded to bits with the syn_noarrayports attribute within Synplify. Please see (Xilinx Answer 504). Also, within CORE Generator or Logiblox, select the bus-notation as "[]". Please read (Xilinx Answer 4041) for a description of generating CORE Generator modules.

AR# 4891
Date 05/14/2014
Status Archive
Type General Article
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