AR# 4930

FPGA Express 2.1.3 - Cannot allocate CLK to BUFG using Constraints Editor

Description

Keywords:
Express, 9500, BUFG, CLK, constraints, buffer, clock.

Urgency:
Standard

Description:
When using FPGA Express, one may use the Express Constraints Editor to select
clock buffers to be place on input ports for clock and high fanout signals.

In some cases for XC9500 designs, the FPGA Express Constraints Editor will not
allow the selection of the BUFG. Only BUFGTS and BUFGSR are available.

Solution

The workaround is to instantiate a BUFG in the HDL code.
AR# 4930
Date 08/11/2003
Status Archive
Type General Article