You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
FPGA Express 2.1.3 - Cannot allocate CLK to BUFG using Constraints Editor
Express, 9500, BUFG, CLK, constraints, buffer, clock.
When using FPGA Express, one may use the Express Constraints Editor to select
clock buffers to be place on input ports for clock and high fanout signals.
In some cases for XC9500 designs, the FPGA Express Constraints Editor will not
allow the selection of the BUFG. Only BUFGTS and BUFGSR are available.
The workaround is to instantiate a BUFG in the HDL code.
Was this Answer Record helpful?