It is sometimes useful to use the Synopsys TRANSLATE_OFF and TRANSLATE_ON pragmas in a VHDL design in order to be able to not specify the UNISIM libraries for synthesis but have them for simulation.
This solution record describes what needs to be done to be able to properly use these pragmas with Synopsys FPGA Compiler or Design Compiler.
To make these pragmas effective a Synopsys variable called hdlin_translate_off_skip_text must be set to true (this variable is defaultly false). The easiest way to do this is to add the following line to your .synopsys_dc.setup file:
hdlin_translate_off_skip_text = true
With this variable set to true, all text within the pragmas will be ignored during synthesis.
These pragmas can be specified on one of two ways.