AR# 4963: FPGA Express 3.x: How to access special IOB components for Virtex/E
FPGA Express 3.x: How to access special IOB components for Virtex/E
Keywords: Virtex, Express, IOB, IBUF, OBUF, IFD, OFD, voltage, standard
General Description: The Virtex/E and Spartan-II architectures have special Select I/O components that allow users to specify the voltage standards each pin must have. This solution explains how to access these components when using FPGA Express for synthesis.
These special IOB components exist in the FPGA Express synthesis library but must be instantiated in your HDL code. The components are IBUF, IBUFG, IOBUF and OBUF, and the names are followed by an underscore and then the voltage standard. For example:
IBUF_GTL IBUFG_PCI66_3 IOBUF_HSTL_IV OBUF_LVCMOS2
A complete list of components understood by FPGA Express can be found in the \lib\virtex directory under the FPGA Express tree (%XILINX%\synth for Foundation users). FPGA Express will understand these components and will not attempt to place any I/O logic on these ports:
Warning: Existing pad cell '/ver1-Optimized/U1' is connected to the port 'clk' - no pads cells inserted at this port. (FPGA-PADMAP-1)
FPGA Express does not merge flip flops into IOBs for Virtex families. Therefore, you have two options if you wish to have this done. 1. Use the map -pr switch to globally (for inputs, outputs, or both) merge flops into IOBs, or 2. Instantiate library primitives (FDCE, FDPE) and attach the IOB=TRUE attribute in your HDL code. See (Xilinx Solution 4392) for more information about attribute passing in FPGA Express.
FPGA Express 3.4 will add the new standards unique to Virtex-E. Also included in that release will be the ability to set these voltage standards from within the Constraints Editor.