General Description: When creating an adder or subractor with a single bit carry-in signal, one cannot simply code A + B + Cin (where A and B are N bits wide, and Cin is a single bit carry in signal), as this will produce two N-bit counters.
Use the following examples to infer a carry-in signal for the carry chain built by FPGA Express.
--VHDL Example --'dummy' signal will be removed
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity add_vhd is port(a, b : in std_logic_vector(15 downto 0); cin : in std_logic; sum : out std_logic_vector(15 downto 0)); end add_vhd;
architecture behav of add_vhd is signal dummy : std_logic_vector(16 downto 0); begin dummy <= (a & cin) + (b & cin); sum <= dummy(16 downto 0); end behav;
//Verilog Example //'dummy' signal will be removed