We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 4983

4.2i Foundation - Errors: "Missing port 'G' in 'C182(GND)'" and "NGDBuild:181 -logical block "name" of type "GND" is unexpanded"


Keywords: Virtex, Foundation, Express, macro, HDL, GND, G, basnu:93, 9500, 95

Urgency: Standard

General Description:
The following problem may be seen within Foundation schematic projects that target Virtex and 9500 CPLD devices -- if you are using an HDL macro, you may see the following message in the console when the schematic is exported to EDIF:

"Conv: Missing port 'G' in 'C182(GND)'."

Then, when the design is implemented, the Translate phase (NGDBuild) will report the following error:

"ERROR:NGDBuild:181 - logical block "name" of type "GND" is unexpanded."


This problem occurs when the Aldec EDIF netlister re-writes an EDIF file that was written by FPGA Express.

You can work around this issue by preventing Foundation from touching the macro EDIF file. This is done by adding an attribute to the macro symbol as follows:

- In the schematic editor, double-click on the macro symbol to open the Symbol Properties.
- In the Parameters section, use the pull-down that is next to the Name field to select "$EXPORT".
- In the Description field, enter "NO" and click the Add button. Click "OK" to accept.

When you implement the design, you will see the following message in the console:

"Conv: Macro `<my_macro>' not exported, property $EXPORT=NO"
AR# 4983
Date 08/12/2003
Status Archive
Type General Article