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AR# 50054

7-Series - OSERDESE2 - What should the TBYTE_CTL and TBYTE_SRC attributes be set to? What could cause my OBUF to unexpectedly Tristate?


In the OSERDESE2 instantiation template the following attributes are available:

TBYTE_CTL => "FALSE", -- Enable tristate byte operation (FALSE, TRUE)
TBYTE_SRC => "FALSE", -- Tristate byte source (FALSE, TRUE)

How should they be set? What arethe effects if they are incorrectly set?


These attributes should be set to FALSE for all use cases where you manually instantiate the OSERDESE2; these attributes are used by MIG and the user should not have to change them.

Note: Some synthesis tools may incorrectly set these attributes to TRUE. If the OLOGIC block in FPGA editor shows these as TRUE, but the MIG design or their design intend them to be FALSE, an IOB may incorrectly tristate.
AR# 50054
Date 02/27/2013
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7