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AR# 50086

MIG 7 Series v1.5 DDR3 - Updated Trace Matching Requirement for CK/CK# and DQS/DQS#

Description

Starting with the release of MIG v1.5, the 7 Series FPGAs Memory Interface User Guide (UG586) includes the following trace guideline:

  • The electrical delay of CK/CK# must be at least 150 ps or greater than all DQS/DQS# signals.

Previously, the documented trace guideline was for CK/CK# to be longer than DQS/DQS#, but an amount was not specified.

This answer record details the change in this guideline, if 150 ps is a requirement, and why the guideline exists.

Solution

The additional delay between CK/CK# and DQS/DQS# adds calibration margin. However, the documented electrical delay of 150 ps or greater is a recommendation rather than a requirement. Existing boards that meet the CK/CK# electrical delay being longer than the DQS/DQS# requirement do not need to be modified. For new boards, it is recommended that the 150 ps difference between CK/CK# and DQS/DQS# be included.

Starting with the MIG v1.6 version of UG586, the guideline will be documented as:

"The CK/CK# signals must arrive at each memory device after the DQS/DQS# signals. The recommended value for additional propagation delay on CK/CK# relative to DQS/DQS# at each memory device is 150 ps or greater, but any value larger than 0 ps and less than 1600 ps is acceptable for all data rates. For DIMM modules, the total CK/CK# and DQS/DQS# propagation delays from the FPGA to the memory components on the DIMM must be accounted for when designing to this requirement."

In general, the overall guideline for CK/CK# to have a longer electrical delay than DQS/DQS# exists to ensure that CK arrives at the SDRAM after DQS. This is required for the Write Leveling stage of calibration. If the CK/CK# electrical delays are not greater than DQS/DQS#, calibration failures can occur during Write Calibration. The expected Write Calibration pattern is 'FF00AA5555AA9966'. When CK is incorrectly shorter than DQS, the read back data pattern is 'XXXXFF00AA5555AA'. This is a one cycle late pattern which cannot be corrected by Write Calibration, therefore causing no pattern detection and Write Calibration failure.

Revision History
08/01/2012 - Updated UG586 documented guideline
05/25/2012 - Initial Release

AR# 50086
Date Created 05/25/2012
Last Updated 11/28/2012
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
IP
  • MIG 7 Series