UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 50101

Logicore IP Aurora 64B66B v6.2 - Targeting Aurora 64B66B core for Hot plug applications using Virtex-6 GTH transceivers

Description

Aurora 64B66B v6.2 does not support hot-plug applications with Virtex-6 GTH transceivers. This answer record gives guidance about how to make Aurora 64B66B work in hot-plug applications.

Solution

LINK_RESETlogicavailable inthe CLOCK_CORRECTION_CHANNEL_BONDING module can be leveraged to detect hot-plug conditions. These signals will get asserted when there is no valid_btf character receivedfora pre-determined number of cycles.This helps in detecting the cable un-plug condition. Connect the LINK_RESET signal to the RX_PCS_CDR_RESET_IN signal of the transceiver so that GTH is reset when there is a cable un-plug condition.

FollowingAurora modules need some modifications to acheive hot-plug.

  1. CLOCK_CORRECTION_CHANNEL_BONDING
  2. RX_GEARBOX
  3. aurora_64b66b_v6_2_WRAPPER

1. CLOCK_CORRECTION_CHANNEL_BONDING:

//assign LINK_RESET = 2'h0;
assign LINK_RESET = {link_reset_1,link_reset_0};

2. RX_GEARBOX:

// assign `DLY hdr_valid = ( odd && ({doutb[65],doutb[64]} == 2'b10 || {doutb[65],doutb[64]} == 2'b01) ) ? 1'b1 :1'b0;
assign `DLY hdr_valid = odd ? 1'b1 : 1'b0;

3. aurora_64b66b_v6_2_WRAPPER:

Declare the following wires - rx_pcs_cdr_reset, link_reset_c, resetdone_i

wire rx_pcs_cdr_reset;
wire[1:0]link_reset_c;
wire resetdone_i;

Code Edits:

// assign gth_tx_reset_comb_i = !tx_pcs_resetdone_i | RESET;
// assign rx_gb_reset_i = rx_pcs_cdr_resetdone_i && !RXRESET_IN;
// assign not_rx_pcs_cdr_resetdone_i = !rx_pcs_cdr_resetdone_i;

assign gth_tx_reset_comb_i = !resetdone_i | RESET;
assign rx_gb_reset_i = resetdone_i && !RXRESET_IN;
assign not_rx_pcs_cdr_resetdone_i = !resetdone_i;
assign rx_pcs_cdr_reset = link_reset_c[0];
assign resetdone_i=rx_pcs_cdr_resetdone_i & tx_pcs_resetdone_i;

AURORA_64B66B_V6_2_QUAD #
(
// Simulation attributes
.QUAD_SIM_GTHRESET_SPEEDUP (SIM_GTHRESET_SPEEDUP)
)
quad2_aurora_64b66b_v6_2_i
(
..
..
.RX_PCS_CDR_RESET_IN (rx_pcs_cdr_reset),
);
RX_GEARBOX #
(
.SYNC_CHAR(64'h7CFF_FFFF_E5AC_A9E8)
)
rx_gb_i
(
..
..
.slip(1'b1)
);\
CLOCK_CORRECTION_CHANNEL_BONDING #
(
.CH_BOND_MAX_SKEW (2'b10),
.CH_BOND_MODE (CHAN_BOND_MODE_0)
)
cbcc_gth_i
(
..
..
.LINK_RESET(link_reset_c)
);

NOTE:
1. The link reset logic assumes the transmission of CC characters from the transmitter, so it is required to ensure that the CC characters are transmitted by the channel partners.
2. The steps outlined in this Answer Record are only given as a guidance to customers. Xilinx has no roadmap to have this feature as part of the core.
Revision History

10/29/2012 - v1.0 - Initial release

Attachments

Associated Attachments

Name File Size File Type
reference.zip 38 KB ZIP
AR# 50101
Date Created 10/29/2012
Last Updated 03/02/2013
Status Active
Type General Article
Devices
  • Virtex-6 HXT
IP
  • Aurora 64B/66B