Description

Why does the core not behave as expected when Verilog generation is selected?

Solution

This is a known issue where the GUI parameters MAX_COUNT and FIFO_SET_POINT are not being properly passed down to the Verilog wrapper file (*_synth.v). There is also a problem where the shift_reg_27x16.v is missing a statement in the generate statement.

These issues have been address in ISE 14.3 Asynchronous Sample Rate Converter (ASRC) v1.0. You can regenerate Asynchronous Sample Rate Converter (ASRC) v1.0 in 14.3 and later, and these changes will be automatically included.

To work around this issue, change *_synth.v (lines 71-73):

From:
.C_FAMILY("virtex6"),
.FIFO_SET_POINT(000010000),
.MAX_COUNT(00001111111111)

To:
.C_FAMILY("virtex6"),
.FIFO_SET_POINT(16),
.MAX_COUNT(1023)

And change shift_reg_27x16.v (line 70):

From:
begin

To:
begin:shift_reg_gen

For a detailed list of LogiCORE IP Asynchronous Sample Rate Converter (ASRC) Release Notes and Known Issues, see (Xilinx Answer 47209).

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