AR# 50154

LogiCORE IP Asynchronous Sample Rate Converter (ASRC) v1.0 - Why does the core not behave as expected when Verilog generation is selected?

Description

Why does the core not behave as expected when Verilog generation is selected?

Solution

This is a known issue where the GUI parameters MAX_COUNT and FIFO_SET_POINT are not being properly passed down to the Verilog wrapper file (*_synth.v).

There is also a problem where the shift_reg_27x16.v is missing a statement in the generate statement.

These issues have been address in ISE 14.3 Asynchronous Sample Rate Converter (ASRC) v1.0. 

You can regenerate Asynchronous Sample Rate Converter (ASRC) v1.0 in the 14.3 release and later versions, and these changes will be automatically included.

To work around this issue, change *_synth.v (lines 71-73):

Original Version:

.C_FAMILY("virtex6"),
.FIFO_SET_POINT(000010000),
.MAX_COUNT(00001111111111)

New Version:

.C_FAMILY("virtex6"),
.FIFO_SET_POINT(16),
.MAX_COUNT(1023)

And change shift_reg_27x16.v (line 70):

Original Version:

begin

New Version:

begin:shift_reg_gen


AR# 50154
Date 07/11/2018
Status Archive
Type General Article
Devices
IP