Why does the core not behave as expected when Verilog generation is selected?
This is a known issue where the GUI parameters MAX_COUNT and FIFO_SET_POINT are not being properly passed down to the Verilog wrapper file (*_synth.v).
There is also a problem where the shift_reg_27x16.v is missing a statement in the generate statement.
These issues have been address in ISE 14.3 Asynchronous Sample Rate Converter (ASRC) v1.0.
You can regenerate Asynchronous Sample Rate Converter (ASRC) v1.0 in the 14.3 release and later versions, and these changes will be automatically included.
To work around this issue, change *_synth.v (lines 71-73):
And change shift_reg_27x16.v (line 70):