The core and example design contain ports (signals) specific to Tandem Configuration. These signals provide handshaking between the first stage (the core) and the second stage (user logic). These signals can coordinate events in the user application. Following is some additional information about these signals:
In addition to these interface signals, the PCIe IP module interface replicates the ports for the ICAP (Tandem PCIe only) and STARTUP blocks, as these blocks are instantiated within the IP core. Look for the icap_* and startup_* ports to connect any user application to these blocks. The only requirement is that the user application must not access these ports until user_app_rdy has been asserted, meaning the design is fully operational.