AR# 50166


LogiCORE IP Serial RapidIO Gen2 - Debugging and Packet Analysis Guide


This answer record provides a debugging and packet analysis guide for LogiCORE IP Serial RapidIO Gen2 Core in a downloadable PDF to enhance its usability. Answer Records are Web-based content that are frequently updated as new information becomes available. Visit this answer record to obtain the latest version of the PDF.


Please download the LogiCORE IP Serial RapidIO Gen2 - Debugging and Packet Analysis Guide (see the PDF file at the end of this solution).

This document describes techniques for debugging issues related to LogiCORE IPSerial RapidIO Gen2 Core. When you are debugging SRIO issues, you should have a clear understanding of the flow of packets through the different interfaces of your design. You should be able to identify what types of packets are seen on those interfaces and correctly decode them by checking the contents of the packets. This document provides a detailed description of tracking SRIO packets (Control Symbols and Data Characters) on different interfaces in the core.

The main objective of this document is to help you debug your design by going into the low level details of the core. The packet and signal analysis have been described based on the simulation of the example design provided along with the generation of the core in the CORE Generator tool. However, the same concept also applies when debugging issues in hardware using the ChipScope tool.


Associated Attachments

AR# 50166
Date 03/02/2013
Status Active
Type General Article
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