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AR# 50195

SelectIO Design Assistant: Performance - Differential IO Standards


This article is part of the Design Assistant section (Xilinx Answer 50926) of the SelectIO Solution Centre (Xilinx Answer 50924).

Please see the main Performance article for more information on I/O performance (Xilinx Answer 47284).

This Answer Record covers the following:

  • How are Differential I/O standards defined by Xilinx?
  • What are the main performance specifications for Differential I/O standards?


Differential I/O standards:

Differential signaling is a method of transmitting data between two devices using two complementary signals, sent on two separate traces.
The two signals are then 'subtracted' by the receiver so that the logic level is detected based on the difference between the two signals.
Because the receiver only cares about the difference between the signal, the variations in the ground plane and noise on the individual signals are cancelled out.
Information on the behavior of the Differential I/O standards is given in the device datasheets.

For inputs, Xilinx specifies a range for the common mode voltage, VICM. This is the voltage that the differential signal varies or swings around.
The other important specification is the VIDIFF. This is the difference between the two signals in the pair. It is given by Vp-Vn when Vp is high and Vn- Vp when Vm is high.

For outputs, Xilinx specifies a range of values for the common mode output voltage. This is the value of the 'common' voltage that the two signals in the pair vary around.
We also specify the difference in the voltage of the two signals in the pair. It is given by Vp-Vn when Vp is high and Vn - Vp when Vn is high. 

Xilinx also gives the VOL and VOH levels. VOL is the minimum output voltage for each of the signals, and VOH this is the maximum output voltage for either of the signals in the pair. 

These specifications must be compared to the corresponding specification at the transmit/receive device to ensure that the link will work.

Shown here is a LVDS signal: The Common mode, differential Swing and VOL VOH are shown.


In many cases, the differential input does not operate in the bank VCCO domain. This can give extra flexibility when placing differential input buffers.

This is discussed in (Xilinx Answer 11906).

You should also look at these two answers for guidance on placing LVDS in different 7 Series bank types:

(Xilinx Answer 40191) - LVDS Compatibility Between LVDS_25 and LVDS.

(Xilinx Answer 41408) - How to Place LVDS in a High Performance Bank.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47284 SelectIO Design Assistant: Performance N/A N/A
AR# 50195
Date 06/02/2017
Status Active
Type Solution Center
  • FPGA Device Families
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