We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 50196

SelectIO Design Assistant: Performance - complementary single-ended I/O Standards


This Article forms part of the Performance section of the Design Assistant (Xilinx Answer 50926) in the SelectIO Solutions Center (Xilinx Answer 47284).

Please see the main Performance article for more information on I/O performance: (Xilinx Answer 47284).

This article will Discuss:

How are complementary single-ended I/O standards defined?

What are the main performance specifications for complementary single-ended I/O standards?


Complementary single-ended I/O standards:

Complementary single-ended I/O standards such as DIFF_SSTL and DIFF_HSTL take advantage of the common mode voltage rejection of differential I/O standards while still having the low voltage swing of the single ended versions of the standards.

This Answer Record gives details of how Xilinx specifies the performance of these I/O standards.

Common Mode / Signal Crossing:

Like all differential I/O standards, the signal has a given common mode voltage range. This specification is often referred to as Vix for inputs and Vox for outputs. This represents the crossing voltage for the two signals in the pair. 

Usually the Vx is the same as VREF for the Single ended version of the I/O standards. A min/max value for the crossing voltage is often specified.

For example in a standard like Differential SSTL15, Xilinx specifies that the crossing point for an input signal needs to be in the range VREF-0.175V < VREF < VREF+0.175V. 

In the case of an output, the crossing point needs to be in the range VREF-0.15V < VREF < VREF+0.15V.

Differential Voltage:

In all cases the differential voltage is the difference in voltage between the Q and /Q side of the pair.

VOH/VOL Levels

Xilinx tends to specify VOL and VOH levels for the complementary single-ended buffers. These figures are the single ended Logic levels for the individual I/Os in the Differential pair. 

Its important to remember in a case where the complementary single-ended pair is acting as an output, then physically in hardware what you have is two single ended SSTL/HSTL buffers driving in opposite directions.

This example shows a DIFF_SSTL18 signal on Virtex-6. The specifications for the complementary single-ended signals are highlighted.


Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47284 SelectIO Design Assistant: Performance N/A N/A
AR# 50196
Date 06/02/2017
Status Active
Type Solution Center
  • FPGA Device Families
Page Bookmarked