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AR# 50197

SelectIO Design Assistant: Performance - Factors Affecting Performance

Description

This Answer Record covers the following:

  • What factors affect the performance of Xilinx I/Os
  • What considerations should be taken when designing an I/O link in the system

Please see the main Performance article for more information on I/O performance: (Xilinx Answer 47284)

This article is part of the Design Assistant section (Xilinx Answer 50926) of the SelectIO Solution Centre (Xilinx Answer 50924).

Solution

Factors Affecting I/O Performance:

I/O performance is affected by a number of factors. The main thing to consider is what sort of line the I/O is connected to. 

For example if the line is not terminated properly then you will see reflections on the line. 

If the I/O driving the line does not have a large enough drive strength then you will see the reflections on the line cause the signal to step up to the VIH level rather than rise. 

Conversely if the I/O drive strength is too large then you will see overshoot at the receiver and the signal will take time to settle to the correct level. 

So it is critical to impedance match the line. For more information on terminating the line, see (Xilinx Answer 47225)


The I/O will be affected by Temperature and Supply Voltage. So it is important to maintain the proper VCCO levels outlined in the datasheet for each IOSTANDARD.

In 7 Series, there is the option to drive the VCCAUX_IO rail at 2V rather than 1.8V. This yields higher data rates on certain types of memory interfaces.

For information on whether there is any risk to run the interface slower when VCCAUX_IO is set to 2V, see (Xilinx Answer 42765).

Another issue for I/O performance is the SSO phenomenon. When output drivers switch simultaneously, they can cause a voltage drop in the chip/package power distribution. 

This switching momentarily raises the ground voltage within the device relative ground on the board.

This shift in the ground potential is known as simultaneous switching noise (SSN) or ground bounce. For further information on SSN see (Xilinx Answer 31905)


A common question is what are the input and output capacitances for a particular device and package?

(Xilinx Answer 13669) gives details on how to determine pin and I/O capacitance for a given device and package.

Another frequent question is about the amount of leakage current on the I/O pins. 

(Xilinx Answer 38957) details some issues with Virtex 4/5/6 where you might see leakage current on the differential pairs due to excessive VIN.

Spartan-6 allows users to select either 2.5V or 3.3V for the VCCAUX rail. 

(Xilinx Answer 39234) details the reasons for picking one VCCAUX value over another and explains some of the differences in performance.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47284 SelectIO Design Assistant: Performance N/A N/A

Associated Answer Records

AR# 50197
Date 06/02/2017
Status Active
Type Solution Center
Devices
  • FPGA Device Families
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