Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)
When Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 is generated for Gen1/Gen2 speed and the performance level in the GUI is set to Extreme, it results in incorrect core functionality.
This is a known issue to be fixed in a future release of the core.
Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
06/06/2012 - Initial release