Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)
According to PCI Express Base Specification v3.0, Secondary PCI Express Extended Capability must be enabled by default in Gen3 core configuration. This is not the case in the current core release. This issue could lead the core to link up in Gen2 speed instead of Gen3 speed.
This is a known issue to be fixed in a future release of the core. To work around this issue, theNextCap pointer of the last enabled extended Capability must point to the Secondary PCIe Cap (300h). If no additional extended capabilities are enabled, make the following modification:
From:
*_AER_CAP_NEXTPTR = 12'h000
To:
*_AER_CAP_NEXTPTR = 12'h300
Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Revision History
01/08/2013 - Added workaround
06/04/2012 - Initial release
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 47441 | Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7 | N/A | N/A |
| AR# 50232 | |
|---|---|
| Date | 02/03/2013 |
| Status | Active |
| Type | Known Issues |
| Tools |
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| IP |
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