AR# 50301


MIG 7-Series DDR3/DDR2 - Usage of mc_odt[1:0]


The 7 series MIG controller to PHY interface includes a 2-bit mc_odt bus. How is this 2-bit bus used to control the ODT pin going to the memory?


The controller to PHY interfaces includes one ODT signal per rank (mc_odt[1:0]). The controller asserts the appropriate mc_odt (according to rank being accessed) signal the entire time we_n is asserted for write(s), plus one additional slow/fabric clock cycle (bufg clock domain). Therefore, for a single write command when loading the Address/Control OUT_FIFOs, the mc_odt[x] is asserted fortwo PHY Control Words (two slow/fabric clock cycles). This can be seen in a simulation of the provided MIG 7 Series Example Design. Depending on the PHY Control Word slot assignment for the write command, ODT may be asserted a cycle earlier than the write command, which is acceptable.

CWL does not come into play from the controllers perspective because the ODT on and ODT off (internal RTT termination) are defined as CWL-2 in the DDR3 SDRAM spec. Thus, the Xilinx MIG 7 Series controller and custom controllers need not worry about timing the ODT with respect to CWL. The extra fabric clock cycle in 4:1 mode accounts for the -2 and allows time for the write data to clear the DQ bus.
AR# 50301
Date 11/28/2012
Status Active
Type General Article
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