UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
Page Bookmarked
  1. Xilinx - All Programmable
  2. Support
  3. AR# 50331: Netgen - single MAX delay is present in SDF when no timing constraints are provided

AR# 50331

Netgen - single MAX delay is present in SDF when no timing constraints are provided

Description

If netgen is performed without PFC or with PCF containing no timing constraints, the SDF file contains only max delay values.
 
The below is an example of comparison SDFs with and without a timing constraint.
 
With timing constraint:

(CELL (CELLTYPE "X_FF")
(INSTANCE count_3)
(DELAY
(ABSOLUTE
(PORT CLK (106:115:115)(106:115:115))
(PORT I (22:24:24)(22:24:24))
(PORT RST (680:693:733)(680:693:733))
(IOPATH CLK O (239:260:260)(239:260:260))
(IOPATH RST O (527:573:573)(527:573:573))

 
Without timing constraint:

(CELL (CELLTYPE "X_FF")
(INSTANCE count_3)
(DELAY
(ABSOLUTE
(PORT CLK ( 115 )( 115 ))
(PORT I ( 24 )( 24 ))
(PORT RST ( 733 )( 733 ))
(IOPATH CLK O ( 260 )( 260 ))
(IOPATH RST O ( 573 )( 57 )

 

Solution

This is an expected behavior and is seen for all devices.

When the .ucf file is not provided/empty, the .pcf file is empty.


In this case the SDF file generated does not need to be timing aware and you can only perform a default analysis while running timing simulation using the MAX values (worst case) which are only present in the file. 

These are the worst delays which would be used by the tool while running simulation.

AR# 50331
Date 01/21/2015
Status Active
Type General Article
Devices
  • CPLD Device Families
  • FPGA Device Families
Tools
  • ISE
  • ISE Design Suite