AR# 50333

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1/Vivado 2012.1) - Core Configuration GUI Incorrectly Selects 62.5 MHz for x4, 2.5 GT/s and 64-bit Interface Width

Description

Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

In the Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 core configuration GUI, when the following parameters are selected, the GUI incorrectly selects AXI-ST Interface Frequency as 62.5 MHz.Lane Width - x4, Link Speed - 2.5 GT/s, Interface Width - 64-bit

In the product guide, the only supported AXI-ST interface frequencies are 125 MHz and 250 MHz for 2.5 GT/s, x4 and 64-bit interface width core configuration.

Solution

This is a known issue to be fixed in a future release of the core. In order to select the supported frequency for 2.5 GT/s, x4 and 64-bit interface width core configuration, please check (Xilinx Answer 50183).

NOTE: "Version Found" refers to the version in which the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
06/06/2012 - Initial Release

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Linked Answer Records

Master Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
47441	Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7	N/A	N/A

AR# 50333
Date	01/21/2013
Status	Active
Type	General Article
Tools	ISE Design Suite - 14.1 Vivado - 2012.1
IP	Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)

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