During the generation of an IP core in CORE Generator, a warning similar to the following is reported depending on the HDL language selected.
WARNING:sim - Component fifo_generator_v9_1 does not have a valid model name for VHDL synthesis
WARNING:sim - Component fifo_generator_v9_1 does not have a valid model name for Verilog synthesis
Why does this occur?
The IP core appears to work correctly. Can the warning be ignored?
This warning can be ignored. The CORE Generator is not properly reconciling the top level name when checking the existence of the synthesis sources.
The issue has been resolved in ISE DesignSuite 14.3