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  3. AR# 50338: 14.2 Core Generator - IP cores generation gives: WARNING:sim - Component does not have a valid model name for VHDL/Verilog synthesis

AR# 50338

14.2 Core Generator - IP cores generation gives: WARNING:sim - Component does not have a valid model name for VHDL/Verilog synthesis

Description

During the generation of an IP core in CORE Generator, a warning similar to the following is reported depending on the HDL language selected.

WARNING:sim - Component fifo_generator_v9_1 does not have a valid model name for VHDL synthesis

or

WARNING:sim - Component fifo_generator_v9_1 does not have a valid model name for Verilog synthesis

Why does this occur?

The IP core appears to work correctly. Can the warning be ignored?

Solution

This warning can be ignored. The CORE Generator is not properly reconciling the top level name when checking the existence of the synthesis sources.

The issue has been resolved in ISE DesignSuite 14.3

AR# 50338
Date 12/14/2012
Status Archive
Type Known Issues
Tools
  • ISE Design Suite - 14.1
  • ISE Design Suite - 14.2