Open your design (i.e., synthesized or implemented) in the PlanAhead tool (not Vivado), and type write_xdc in the Tcl command window to write out an XDC file.
The newly created XDC file will have both the physical and timing constraints. The physical constraints were converted correctly and should be copied to your design.xdc file. The timing constraints should not be used and should be removed or ignored. Xilinx recommends creating the timing constraints manually through the Vivado design tools or a text editor for the design.xdc file.