UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 50379

7 Series FPGAs - What are the Addresses and Values for Dynamic Reconfiguration of the MMCM/PLL through the DRP?

Description

The DRP functionality for the 7 Series FPGA MMCM and PLL is supported through an Application Note and associated reference design.

Solution

XAPP888 MMCM and PLL Dynamic Reconfiguration, (https://www.xilinx.com/support/documentation/application_notes/xapp888_7Series_DynamicRecon.pdf), describes the DRP feature in detail.

A HDL reference design is provided along with the Application Note. The reference design uses a state machine to drive the DRP and ensures the registers are controlled in the correct sequence.

The register map is build into the _drp_func.h in the XAPP888 but will not be provided to customers outside of the XAPP implementation.

AR# 50379
Date 06/13/2017
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7