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AR# 50450

Vivado Timing - Clock Pessimism Removal: Understanding, Calculating and Determining CPR

Description

What is Clock Pessimism Removal (CPR) and how it is calculated?

Solution

  • In static timing analysis, two metrics are typically checked: the setup and the hold. This explanation is from the vantage point of the setup check.  
  • Data and clocking paths within the FPGA carry a probabilistic delay whose bounds are determined by process, voltage, and temperature variation (PVT).
  • There are two processes, fast and slow. Both have a minimum and maximum bound for path delay.
  • The tools use maximum data path and minimum clock path in order to find the worst-case setup scenario.

Referring to figure 1:

  • There is a common clock path before the clock splits and goes to the respective flops.
  • This means that the destination path will apply the minimum path delay and the source path will apply the maximum.
  • The problem is that these paths were connected upstream.
  • For this common path, it is not possible to apply both the minimum and maximum delay.
  • CPR accounts for this problem by taking the difference between the maximum and minimum values. In other words: CLK_COMMONdest - CLK_COMMONsource
  • This difference is factored into the slack calculation. 

Figure 1: Setup and Hold CPR Scenarios.

 

 

 

With Respect to a Real Life Example:

  • From the report below, the CPR should be -0.353 ns.
  • Again, CPR = CLK_COMMONdest - CLK_COMMONsource
  • In this case, the common clocking path begins at the PAD (AG10) and ends at the output of the BUFG (BUFGCTRL_X0Y1).
  • After this point, the path splits into two respective slices. In the report below, the CPR is said to be -2.534 ns, which is incorrect.


CLK_COMMONdest = 9.948 ns - 5 ns = 4.498 ns (Account for the next clock edge by subtracting 5 ns)
CLK_COMMONsource  = 5.301 ns
CPR CLK_COMMONdest - CLK_COMMONsource = 4.498 ns - 5.301 ns = -0.353 ns.

The report below shows incorrect CPR. This problem is now fixed (2012.3).

This is from the Error Message

------------------------------ 
INFO: 
[Timing-91] UpdateTimingParams: Estimated, Speed grade: -1, Delay Type: max, Constraints type: SDC.
INFO: [Timing-78] ReportTimingParams: -max_paths 1 -nworst 1 -transition rf -delay_type max -sort_by slack. ------------------------------------------------------------------------------------ | Report : timing
| Design : blastpn_fpga0
| Part : Device=7k325t Package=ffg900 Speed=-1 (PREVIEW 1.04 2012-04-11)
| Version : Vivado v2012.1 (64-bit) Build 179419 by xbuild on Thu Apr 26 11:43:29 MDT 2012
| Date : Thu Jun 14 15:14:10 2012
| Command : report_timing -from i_blast_common/i_ddr3_wrapper_1/i_mig_7series_v1_4/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.if_empty_r_reg/Q -to {i_blast_common/i_ddr3_wrapper_1/i_mig_7series_v1_4/u_memc_ui_top_std/u_ui_top/ui_rd_data0/not_strict_mode.app_rd_data_reg[64]/D} ------------------------------------------------------------------------------------ Slack (VIOLATED) : -4.895ns Source: i_blast_common/i_ddr3_wrapper_1/i_mig_7series_v1_4/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.if_empty_r_reg/Q
(rising edge-triggered cell FDCE clocked by clk_pll_1 {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: i_blast_common/i_ddr3_wrapper_1/i_mig_7series_v1_4/u_memc_ui_top_std/u_ui_top/ui_rd_data0/not_strict_mode.app_rd_data_reg[64]/D
(rising edge-triggered cell FDCE clocked by clk_pll_1 {rise@0.000ns fall@2.500ns period=5.000ns})
Path Group: clk_pll_1
Path Type: Max at Slow Process Corner
Requirement: 5.000ns
Data Path Delay: 6.817ns (logic 0.539ns (7.907%) route 6.278ns (92.093%))
Logic Levels: 5 (LUT2=2 LUT3=1 LUT4=1 LUT6=1)
Clock Path Skew: -3.024ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 6.663ns
Source Clock Delay (SCD): 7.153ns
Clock Pessimism Removal (CPR): -2.534ns
Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.081ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_pll_1 rise edge)
0.000 0.000 r
AG10 0.000 0.000 r CLK_HPCLK_P
AG10 IBUFDS (Prop_ibufds_I_O) 1.036 1.036 r i_blast_common/i_ibufds_sys_clk0/O
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN2_CLKOUT3)
1.317 2.353 r i_blast_common/i_ddr3_wrapper_1/i_mig_7series_v1_4/u_ddr3_infrastr
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 2.948 5.301 r i_blast_common/i_ddr3_wrapper_1/i_mig_7series_v1_4/u_ddr3_infrastructure/u_bufg_clkdiv0/O
SLICE_X152Y94 net (fo=4991) 1.852 7.153 r i_blast_common/i_ddr3_wrapper_1/i_mig_7series_v1_4/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.if_empty_r_reg/C ------------------------------------------------------------------- -------------------< SLICE_X152Y94 FDCE (Prop_fdce_C_Q) 0.308 7.461 r i_blast_common/i_ddr3_wrapper_1/i_mig_7series_v1_4/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.if_empty_r_reg/Q SLICE_X150Y70 LUT4 (Prop_lut4_I2_O) 1.484 8.945 r i_blast_common/i_ddr3_wrapper_1/i_mig_7series_v1_4/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/i_134281_7618/O SLICE_X114Y77 LUT2 (Prop_lut2_I1_O) 1.691 10.636 r i_blast_common/i_ddr3_wrapper_1/i_mig_7series_v1_4/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/i_134281_10513/O SLICE_X114Y77 LUT2 (Prop_lut2_I0_O) 0.286 10.922 r i_blast_common/i_ddr3_wrapper_1/i_mig_7series_v1_4/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/i_134281_11708/O SLICE_X127Y77 LUT6 (Prop_lut6_I5_O) 0.757 11.679 r i_blast_common/i_ddr3_wrapper_1/i_mig_7series_v1_4/u_memc_ui_top_std/u_ui_top/ui_rd_data0/i_134281_11854/O SLICE_X150Y88 LUT3 (Prop_lut3_I1_O) 2.325 14.004 r i_blast_common/i_ddr3_wrapper_1/i_mig_7series_v1_4/u_memc_ui_top_std/u_ui_top/ui_rd_data0/i_134102_12146/O SLICE_X150Y88 net (fo=1) 0.000 14.004 r i_blast_common/i_ddr3_wrapper_1/i_mig_7series_v1_4/u_memc_ui_top_std/u_ui_top/ui_rd_data0/not_strict_mode.app_rd_data_reg[64]/D SLICE_X150Y88 FDCE (Setup_fdce_C_D) -0.034 13.970 i_blast_common/i_ddr3_wrapper_1/i_mig_7series_v1_4/u_memc_ui_top_std/u_ui_top/ui_rd_data0/not_strict _mode.app_rd_data_reg[64] ------------------------------------------------------------------- ------------------- (clock clk_pll_1 rise edge)
5.000 5.000 r
AG10 0.000 5.000 r CLK_HPCLK_P
AG10 IBUFDS (Prop_ibufds_I_O) 0.935 5.935 r i_blast_common/i_ibufds_sys_clk0/O
PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN2_CLKOUT3)
1.231 7.166 r i_blast_common/i_ddr3_wrapper_1/i_mig_7series_v1_4/u_ddr3_infrastructure/plle2_i/CLKOUT3
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 2.782 9.948 r i_blast_common/i_ddr3_wrapper_1/i_mig_7series_v1_4/u_ddr3_infrastructure/u_bufg_clkdiv0/O
SLICE_X150Y88 net (fo=4991) 1.715 11.663 r i_blast_common/i_ddr3_wrapper_1/i_mig_7series_v1_4/u_memc_ui_top_std/u_ui_top/ui_rd_data0/not_stric
t_mode.app_rd_data_reg[64]/C
clock pessimism -2.534 9.129
clock uncertainty -0.054 9.075 ------------------------------------------------------------------- required time 9.075
arrival time -13.970 ------------------------------------------------------------------- slack -4.895
AR# 50450
Date Created 01/17/2013
Last Updated 08/27/2013
Status Active
Type Known Issues
Devices
  • FPGA Device Families
Tools
  • Vivado Design Suite