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AR# 50471

14.1 XPS - AXI_7series_DDRx 1.04.a - ERROR:HDLCompiler:532

Description

I have a project in XPS 14.1 with axi_7series_ddrx(v1.04a) configured with the DATA WIDTH set  to 72-bit and ECC enabled.

I have selected MT41J256M8XX-107 as the memory part and left the other settings at the default values. 

I am receiving the errors below:

ERROR:HDLCompiler:532 - "C:/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_7series_ddrx_v1_04_a/hdl/ver
ilog/axi_ctrl_reg_bank.v" Line 284: Index <27> is out of range [26:0] for signal <ecc_err_addr_real>.
ERROR:HDLCompiler:532 - "C:/Xilinx/14.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_7series_ddrx_v1_04_a/hdl/ver
ilog/axi_ctrl_reg_bank.v" Line 283: Index <27> is out of range [26:0] for signal <ecc_err_addr_swap_row_bank>.

Solution

The width of "ecc_err_addr_real" and "ecc_err_addr_swap_row_bank" are determined by the parameter P_MC_ERR_ADDR_WIDTH in the top module (for example axi_7series_ddrx.v).

For XPS 14.1, the parameter P_MC_ERR_ADDR_WIDTH in axi_7series_ddrx.v is fixed at 28.

The P_MC_ERR_ADDR_WIDTH should be a calculated value instead of a fixed value as seen below:

localparam P_MC_ERR_ADDR_WIDTH = ((C_CS_WIDTH == 1) ? 0 : P_RANK_WIDTH) + C_BANK_WIDTH + C_ROW_WIDTH + C_COL_WIDTH + P_DATA_BUF_OFFSET_WIDTH;

This issue is resolved in XPS 14.2.

AR# 50471
Date Created 06/17/2012
Last Updated 09/17/2014
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
Tools
  • ISE Design Suite - 14.1