The replace_fpga and uniquify commands must not be used when compiling a Virtex design with Synopsys FPGA/Design Compiler.
The following is an explanation of why the two commands should not be used with Virtex designs:
(1) replace_fpga It was never intended that replace_fpga be used in the Virtex flow, since Virtex synthesizes to LUT's. If you did not choose to use LUT's, the resulting Virtex EDIF file from the synthesis tool would be very large.
(2) uniquify Uniquify cannot be used due to a problem with FPGA Compiler I. Uniquify will remove attributes from library cells. What this generally results in is an EDIF netlist without EQN attributes on the inferred LUTs. This will result in an error in NGDBUILD.
Rather than using uniquify, you should compile the lower level modules first, place a "dont_touch" attribute on them, then compile the top level. This will prevent the lower level modules from being synthesized multiple times.
The .synopsys_dc.setup file must have all the Virtex specific settings in order to write a proper .SEDIF file. A Template for this file (as well as a sample run script for Virtex) can be found in $XILINX/synopsys/examples. Specifically, if the edifout_write_properties setting has been modified, this NGDHelpers error may occur.