AR# 50550

Description

When running an ODDR2 simulation for Spartan-6 where the CLK and Data change at the same time, an issue can occur where that the Data out of the ODDR2 is identical to the data at the ODDR2 inputs at the same time:

Solution

This issue is caused by delta delays in the simulator.

If a net is added to the data input of the ODDR2 this will add a delta delay that will resolve the issue.

The following is an example:

Data_IN_Del <= Data_IN

ODDR_inst0 : ODDR2
generic map(
DDR_ALIGNMENT => "C0",
SRTYPE => "ASYNC")
port map (
Q => oddr2_out(0),
C0 => CLK,
C1 => CLK_N,
CE => CE,
D0 => Data_IN_Del,
D1 => '0',
R => Reset,
S => '0'
);

Once this delta delay is added the simulation will be as expected:

The delta delay added by this additional net will not affect the timing or performance in Hardware and so it can be safely left in during implementation of the design.