UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - All Programmable
  2. Support
  3. AR# 50551: MMCME2_ADV Unisim Model is not asserting LOCKED when Simulating with NCSIM

AR# 50551

MMCME2_ADV Unisim Model is not asserting LOCKED when Simulating with NCSIM

Description

The MMCME2_ADV Unisim Model is not asserting LOCKED when Simulating with NCSIM.

Solution

This is a known issue with the MMCME2_ADV Model.


The effect of this issue was observed while simulating a MIG 7 Series (v1.5) example design in Cadence NCSIM 11.1.

Due to the unavailability of the LOCK signal from one of the infrastructure MMCM (mmcm_i), the design was not being calibrated. 


This issue has been resolved in the 14.2 release with an updated model.

AR# 50551
Date 09/24/2014
Status Active
Type General Article
Devices
  • Virtex-7
Tools
  • ISE Design Suite - 14
IP
  • MIG 7 Series
Page Bookmarked