2. Support
  3. AR# 5057: 4.2i Foundation Timing Simulator - Metastable operation not accurately simulated (undefined state persists)
  4. AR# 50577: ISE Simulator : How to set simulator resolution in ISE Project Navigator?

AR# 50577

|

ISE Simulator : How to set simulator resolution in ISE Project Navigator?

Description

How to set simulator resolution in ISE Project Navigator?

Solution

For Verilog Design:

1. Open the ISIM Properties window by Right Clicking on "Simulate Behavioral Model".

2. Use the switch -timescale and set the resolution accordingly in Other Compiler Options. For example "-timescale 1ps/1fs"

Syntax:

-timescale <time_unit /time_precision>
 
This specifies the default timescale for Verilog modules that do not have an effective timescale.

The time_unit is the unit of measurement of delays.

The time_precision is the unit of accuracy.

Both time_unit and time_precision are entered as a number (1|10|100|...) followed by the unit (fs|ps|ns|us|ms|s).
 
The default timescale is 1ns/1ps.
  

For VHDL Design: 

1. Open the ISIM Properties window by Right Clicking on Simulate Behavioral Model.

2. Use the switch -timeprecision_vhdl and set the resolution accordingly in Other Compiler Options. For example "-timeprecision_vhdl 1us"
 
Syntax:
 

-timeprecision_vhdl<time_precision>

This specifies the time precision (unit of accuracy) for all VHDL design units.

The time_precision is entered as a number (1|10|100|...) followed by the unit (fs|ps|ns|us|ms|s).

The default is 1ps.

 

AR# 50577
Date 07/28/2014
Status Active
Type General Article
Devices
Tools
People Also Viewed