2. Support
  3. AR# 5057: 4.2i Foundation Timing Simulator - Metastable operation not accurately simulated (undefined state persists)
  4. AR# 50579: Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (SE 14.1/Vivado 2012.1) - Why are m_axis_cq_tready and m_axis_rc_tready signals 22 bits?

AR# 50579

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (SE 14.1/Vivado 2012.1) - Why are m_axis_cq_tready and m_axis_rc_tready signals 22 bits?

Description

Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

The 7 Series PCIe Gen3 Product Guide (PG023) describes that m_axis_cq_tready and m_axis_rc_tready are 1 bit each in width. However, in the example design source files of the core, these signals are defined as 22 bits.

Solution

The port width of m_axis_cq_tready and m_axis_rc_tready is 22 bits. All pins are functionally identical and need to be driven with the same value.

The signal is 22-bits wide to assist in timing closure.

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
09/25/2012 - Initial release

AR# 50579
Date 08/26/2013
Status Active
Type General Article
Devices
IP