AR# 50617


Design Advisory for the Kintex-7 and Virtex-7 FPGA Production GTX Transceivers


This answer record covers the updates related to 7 series FPGA GTX Transceiver Production Silicon.


1. Bitstream Compatibility between GTX General ES and Production Silicon:

The General ES bitstream generated with v2.1 or earlier version of the 7 series FPGA Transceivers Wizard in ISE 14.1/Vivado 2012.1 or earlier tools, for all Kintex-7 devices and 7VX485T in the Virtex-7 family, cannot be used with GTX production silicon. For GTX bitstream compatibility between General ES and Production for these devices, the 7 series FPGAs Transceivers Wizard version 2.2 or later in ISE 14.2/2012.2 or later must be used. However for any other considerations related to bitstream compatibility, please refer to (Xilinx Answer 50906).

Also, for the optimized CDR attribute settings under certain conditions as described in (Xilinx Answer 51884), the wizard version 2.3 in ISE 14.3/Vivado 2012.3 or later tools must be used.

2. RX_DFE_XYD_CFG Attribute:

The RX_DFE_XYD_CFG attribute must be set to the value of 13'h0000 for GTX production transceivers. The 7 series FPGAs Transceivers Wizard v2.2 in ISE 14.2/Vivado 2012.2 tools generate the wrapper with this updated value. This value also works for General ES Silicon.

3. GTXE2_COMMON Use Mode:

The GTXE2_COMMON use mode change described in (Xilinx Answer 43339) must be followed for GTX production transceivers. The GTXE2_COMMON module must be instantiated even if only the CPLL is being used in the design. Otherwise, BIAS_CFG will be set incorrectly in the software model to 64'h0000000000000000. When using the 7 series FPGAs Transceivers Wizard v2.2 in ISE 14.2/Vivado 2012.2 tools, the GTXE2_COMMON module is automatically instantiated.

4. GTX Transceiver Power-up/Power-down:

The recommended GTX transceiver power-up/power-down sequences between VMGTAVCC, VMGTAVTT, VCCINT must be followed to achieve minimum current draw. Please refer to (Xilinx Answer 47817) for additional details. This recommended power sequencing is now in the Kintex-7 and Virtex-7 FPGAs Data Sheet (DS182 and DS183).

Revision History
10/26/2012 - Updated the bitstream compatibility section to include references to specific devices
10/18/2012 - Updated the bitstream compatibility section
07/20/2012 - Initial release

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AR# 50617
Date 10/26/2012
Status Active
Type Design Advisory
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