The following error occurs when I use the Vivado 2012.2 design tools while sourcing a Tcl script to create a project for 7 series Q devices (defense grade parts) and the 7 series GTX IBERT IP core:
This is a known issue for the Vivado 2012.2 design tools and will be fixed in the next customer release (2012.3).
To work around this issue, use the GUI to create the project and 7 series GTX IBERT core.
The Tcl flow does not work in this case.
This issue does not affect projects targeting commercial or industrial grade 7 series devices.
If you have any questions regarding this issue, please open up a WebCase with Xilinx Technical Support at: