UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 50643

MIG v3.9-3.92 Spartan-6 MCB - Design fails on the SP601 board using CES silicon

Description

Issue Found: MIG v3.9

When using the MIG v3.9-3.92 design on an SP601 board, the design fails in hardware. This issue only occurs when targetting an SP601 board with CES silicon.

Solution

This failure occurs due to a change in the MIG rtl to support Self Refresh with Suspend operation (reference (Xilinx Answer 42802) for more information). As Self Refresh is not used int he SP601 design, revert the change In the infrastructure.v/vhd file asfollows:

From
BUFGCE U_BUFG_CLK1
(
.O (mcb_drp_clk),
.I (mcb_drp_clk_bufg_in),
.CE (locked)
);
To
BUFG U_BUFG_CLK1
(
.O (mcb_drp_clk),
.I (mcb_drp_clk_bufg_in)
);
AR# 50643
Date Created 07/02/2012
Last Updated 07/02/2012
Status Active
Type Known Issues
Devices
  • Spartan-6
IP
  • MIG Virtex-6 and Spartan-6