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AR# 50644

SelectIO Design Assistant: IBIS Models & Simulation


This article deals with IBIS models for I/Os.

IBIS models are a representation of the Xilinx I/O drivers and receivers. They model the I/O behavior using I-V curves for its constituent parts. They do not rely on specific transistor level modelling. 

The main advantage of this is that simulation run times are extremely fast compared to traditional HSPICE models.

This Answer record provides information needed to make use of the IBIS models.

This article is part of the Design Assistant section (Xilinx Answer 50926) of the SelectIO Solution Centre (Xilinx Answer 50924).


The first thing to consider is what information can be derived from the IBIS models. The IBIS Model Background section of the SelectIO Design Assistant will show you what the IBIS simulations can and cannot be used for.

Please see (Xilinx Answer 50653) IBIS Models & Simulations - IBIS Model Background for more information on this.

Once you are more familiar with what is contained in the IBIS model, please see (Xilinx Answer 50645) Using IBIS Models.

For help with IBIS simulation set up see (Xilinx Answer 50954) IBIS Simulation Setup.

There are some limitations to using IBIS models. To learn more about these limitations, please see (Xilinx Answer 50955) IBIS Model Limitations.

For more information on using IBIS_Writer/Write_IBIS please see (Xilinx Answer 50957) IBIS Writer Guide

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AR# 50644
Date 06/02/2017
Status Active
Type Solution Center
  • FPGA Device Families
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