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MIG v3.91 Virtex-6 DDR3/DDR2 - Design fails when "Add I/O Buffers" option is used in XST
The MIG Virtex-6 DDR3/DDR2 design explicitly instantiates I/O primitives into the HDL except for all of the address and control pins in the phy_control_io module.
Because the I/O Buffers are not instantiated for all of the signals, the IOSTANDARDS defined in the UCF are not binding properly to the port.
These failures only occur when the XST option "-iobuf" (Add I/O Buffers) is used.
This issue has been fixed with the 14.2 release for both the Verilog and VHDL designs.
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- MIG Virtex-6 and Spartan-6