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AR# 50701

MIG 7 Series DDR3 - MIG incorrectly assigns two Chip Select (CS) pins to the single rank part MT9JSF25672PZ

Description

Version Found: v1.5
Version Resolved and other Known Issues: See (Xilinx Answer 45195).
 

The MT9JSF25672PZ single rank part incorrectly has two Chip Select (CS) pins.

Solution

Xilinx recommends upgrading to the latest version of MIG to work around this issue.

Alternatively, create a custom memory part using a different single rank part selected as the base part, and then manually entering the timing specifications for the MT9JSF25672PZ. 

You can also work around it by modifying the following parameters:

CS_WIDTH = 1

nCS_PER_RANK = 1

PHY_0_BITLANES = 48'h000_000_000_000, (value depends on pinout and CS placement, refer to UG586 for details)
PHY_1_BITLANES = 48'h000_000_000_000, (value depends on pinout and CS placement, refer to UG586 for details)
PHY_2_BITLANES = 48'h000_000_000_000, (value depends on pinout and CS placement, refer to UG586 for details)
CS_MAP = 120'h000_000_000_000_000_000_000_000_000_0XX, (value depends on CS placement, refer to UG586 for details)


AR# 50701
Date Created 07/11/2012
Last Updated 08/13/2014
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series